
/**
  @file drv_api.h

  @date 2010-02-26

  @version v5.1

  The file implement driver acc IOCTL defines and macros
*/

#ifndef _DRV_API_H_
#define _DRV_API_H_
#ifdef __cplusplus
extern "C" {
#endif
#include "sal.h"
#include "usw/include/drv_tbl_macro.h"
#include "usw/include/drv_error.h"
#include "usw/include/drv_enum.h"
#include "usw/include/drv_struct.h"

/**********************************************************************************
              Define Typedef, define and Data Structure
***********************************************************************************/

#define SDB_DISABLE         0
#define SDB_NORMAL         1
#define SDB_TIMESTAMP    2
#define SDB_MEM_MODEL  3

#ifndef SDB_MODE
#if (defined(TSINGMA_MX) || defined(TSINGMA_GX) || defined(ARCTIC)) && !defined(TSINGMA) && !defined(DUET2)
#define SDB_MODE    SDB_NORMAL
#else
#define SDB_MODE    SDB_DISABLE
#endif
#endif


#define MAX_ENTRY_WORD 128    /**< define table/reg entry's max words */
#define MAX_ENTRY_BYTE 128   /**< define table/reg entry's max bytes */

#define DRV_WB_STATUS_DONE          1
#define DRV_WB_STATUS_RELOADING     2
#define DRV_WB_STATUS_SYNC          3

#define PP_NUM_PER_CORE     drv_vchip_get_core_pp_num(lchip)

#define DRV_IOC_READ        0U
#define DRV_IOC_WRITE      1U
#define DRV_IOC_REMOVE   2U
#define DRV_IOC_MAX        3U

#define DRV_IOC_SLICE_BITS    3
#define DRV_IOC_DIR_BITS      2
#define DRV_IOC_MEMID_BITS    15
#define DRV_IOC_FIELDID_BITS  12
#define DRV_ENTRY_FLAG        0xFFF   /* when fieldid equals this value, it represent
                                          the operation is applied to the whole entry */
#define DRV_ALL_SLICE     0

#define DRV_BYTES_PER_MPLS_ENTRY 8       /* 8 bytes per entry for 34,45 bits*/
#define DRV_BYTES_PER_ENTRY 12        /* 12 bytes per entry for 80 bits*/
#define DRV_LPM_KEY_BYTES_PER_ENTRY 8        /* 8 bytes per entry for 40 bits */
#define DRV_LPM_AD0_BYTE_PER_ENTRY 8        /* IP prefix LPM AD 2W */
#define DRV_LPM_AD1_BYTE_PER_ENTRY 8        /* NAT prefix LPM AD 1W */
#define DRV_ADDR_BYTES_PER_ENTRY 16   /* 16 bytes address per entry for 80 bits*/
#define DRV_BYTES_PER_WORD 4
#define DRV_BITS_PER_WORD 32
#define DRV_WORDS_PER_ENTRY      3     /*(DRV_BYTES_PER_ENTRY/DRV_BYTES_PER_WORD)  3 words per entry for 80 bits*/
#define DRV_LPM_WORDS_PER_ENTRY  2 /*(DRV_LPM_KEY_BYTES_PER_ENTRY/DRV_BYTES_PER_WORD)  2 words per entry for 40 bits*/
#define DRV_HASH_85BIT_KEY_LENGTH   11
#define DRV_HASH_170BIT_KEY_LENGTH   22
#define DRV_HASH_340BIT_KEY_LENGTH   44

#define DRV_IOC_SLICE_MASK     0x7
#define DRV_IOC_DIR_MASK        0x3
#define DRV_IOC_MEMID_MASK   0x7FFF
#define DRV_IOC_FIELDID_MASK  0xFFF
#define DRV_IOC_FIELDID_SHIFT 0
#define DRV_IOC_MEMID_SHIFT  12
#define DRV_IOC_DIR_SHIFT       27
#define DRV_IOC_SLICE_SHIFT    29
#define DRV_IOC_DP_ID_SHIFT    34
#define DRV_IOC_SLICE(cmd)      (((cmd) >> DRV_IOC_SLICE_SHIFT)&DRV_IOC_SLICE_MASK)
#define DRV_IOC_OP(cmd)          (((cmd) >> DRV_IOC_DIR_SHIFT)&DRV_IOC_DIR_MASK)
#define DRV_IOC_MEMID(cmd)    (((cmd) >> DRV_IOC_MEMID_SHIFT)&DRV_IOC_MEMID_MASK)
#define DRV_IOC_FIELDID(cmd)   (cmd & DRV_IOC_FIELDID_MASK)
#define DRV_IOC(dir, memid, fieldid) \
    (((dir) << DRV_IOC_DIR_SHIFT) | \
    ((memid) << DRV_IOC_MEMID_SHIFT) | \
    ((fieldid) << DRV_IOC_FIELDID_SHIFT))
  /*CMD: op-memid-fieldid: [31:29][28:27][26:12][11:0]*/
#define DRV_IOCTL                           drv_ioctl_api
#define DRV_IOCTL_BMP                       drv_ioctl_bmp_api
#define DRV_FIELD_IOCTL                drv_field_ioctl_api
#define DRV_FIELD_IOCTL_BMP                       drv_field_ioctl_bmp_api

#define DRV_IOC_SLICE_BITS    3
#define DRV_IOC_DIR_BITS      2
#define DRV_IOC_MEMID_BITS    15
#define DRV_IOC_FIELDID_BITS  12

 /**/
#define DRV_IOR(memid, fieldid) DRV_IOC(DRV_IOC_READ, (memid), (fieldid))
#define DRV_IOW(memid, fieldid) DRV_IOC(DRV_IOC_WRITE, (memid), (fieldid))
#define DRV_IOD(memid, fieldid) DRV_IOC(DRV_IOC_REMOVE, (memid), (fieldid))

#define DRV_CMD_SID(cmd, sliceid) (cmd | ((1 << (sliceid)) <<  DRV_IOC_SLICE_SHIFT))
#define DRV_CMD_SBMP(cmd, slice_bmp) (cmd | ((slice_bmp) <<  DRV_IOC_SLICE_SHIFT))

#define DRV_CMD_CORE_BMP_SHIFT 6
#define DRV_CMD_CORE_BMP(cmd, core_bmp) (cmd | ((uint64)((core_bmp) << DRV_CMD_CORE_BMP_SHIFT) << DRV_BITS_PER_WORD)) /*used for DRV_IOCTL_BMP*/

#define DRV_CMD_BMP_EN(cmd, pp_en)   \
        (cmd | ((uint64)(((pp_en)<<7) | ((pp_en)<<6) | ((pp_en)<<5) | ((pp_en)<<4) | ((pp_en)<<3) | ((pp_en)<<2) | \
        (((((!DRV_IOC_OP(cmd))<<1)^0x3)) &(((pp_en)<<1)|(pp_en)))) << DRV_BITS_PER_WORD))

#define DRV_CMD_PP_EN(cmd)   \
    (cmd | ((uint64)(0xFC | ((((!DRV_IOC_OP(cmd))<<1)^0x3))) << DRV_BITS_PER_WORD))

#define DRV_CMD_DP_EN(cmd, dp_id)   (cmd | ((uint64)(0xFC |(1<<(dp_id))) << DRV_BITS_PER_WORD))

#define DRV_ACC_BMP_EN(pp_en)  \
     (((pp_en)<<7) | ((pp_en)<<6) | ((pp_en)<<5) | ((pp_en)<<4) | ((pp_en)<<3) | ((pp_en)<<2))

#define DRV_ACC_PP_EN (0xFC)

struct drv_ioctl_param_s
{
    uint32 tbl_id;     /* key table id based on hw block */
    uint32 index;      /* key index based on hw block */
    uint16 entry_len;  /* entry length，for program 1:160 bits, 2:320 bits, 3:480 bits, other is 1 */
    uint16 op_bmp;     /* core[7:6]pp[5:2]dp[1:0] info */
    uint32 ad_tbl_id;  /* ad table id */
    uint32 ad_index;   /* ad index */
    void* p_value;     /* operation data include data mask and valid */
};
typedef struct drv_ioctl_param_s drv_ioctl_param_t;

#define DRV_ACC_DP_EN(dp_id) (0xFC |(1<<(dp_id)))


#define DRV_IOC_DP_ID(cmd) (!(((cmd) >> DRV_BITS_PER_WORD) & 0x1))

#define DRV_INS(ins, entry)  (((ins) << 24)|(entry))

#ifdef EMULATION_ENV
 /*EMU_MODIFY, 0x10: pp2*/
extern uint32 g_drv_oper_bmp;
#define DRV_OPER_BMP_PP_MASK2(BMP) {(BMP) &= g_drv_oper_bmp; if (0 == (((BMP) >> 2) & 0xF)) {(BMP) |= 0x10;}}
#define DRV_OPER_BMP_CONTINUE_PP(pp_id, label) if ( 0 == ((0x1 << (2 + (pp_id))) & g_drv_oper_bmp)) {label;}
#else
#define DRV_OPER_BMP_PP_MASK2(BMP)
#define DRV_OPER_BMP_CONTINUE_PP(pp_id, label)
#endif

typedef uint32 drv_fib_acc_fib_data_t[6];
typedef uint32 drv_fib_acc_rw_data_t[20];
#if 0
typedef uint32 drv_ipfix_acc_fib_data_t[6];
typedef uint32 drv_ipfix_acc_rw_data_t[20];
typedef uint32 max_ds_t[32];
#endif
#if (HOST_IS_LE == 0)

#define DRV_SWAP32(val) (uint32)(val)
#define DRV_SWAP16(val) (uint16)(val)
#else
#define DRV_SWAP32(val) \
    ((uint32)( \
         (((uint32)(val) & (uint32)0x000000ffUL) << 24) | \
         (((uint32)(val) & (uint32)0x0000ff00UL) << 8) | \
         (((uint32)(val) & (uint32)0x00ff0000UL) >> 8) | \
         (((uint32)(val) & (uint32)0xff000000UL) >> 24)))

#define DRV_SWAP16(val) \
    ((uint16)( \
         (((uint16)(val) & (uint16)0x00ffU) << 8) | \
         (((uint16)(val) & (uint16)0xff00U) >> 8)))
#endif


#define DRV_IOW_FIELD(lchip, memid, fieldid, value, ptr) \
    do\
    {\
        drv_set_field(lchip, memid, fieldid, ptr, value);\
    }\
    while(0)

#define DRV_IOR_FIELD(lchip, memid, fieldid, value, ptr) \
    do\
    {\
        drv_get_field(lchip, memid, fieldid, ptr, value);\
    }\
    while(0)

#define DRV_SET_FIELD_ADDR  drv_set_field
#define DRV_GET_FIELD       drv_get_field
#define DRV_SET_FIELD_VALUE(lchip, tbl_id, field_id, entry, value) \
        drv_set_field32(lchip, tbl_id, field_id,(uint32*)(entry), value)

#define DRV_SET_FIELD_V(lchip, tbl_id, field_id, entry, value) \
        drv_set_field32(lchip, tbl_id, field_id,(uint32*)(entry), value)

#define DRV_SET_FIELD_A(lchip, t,f,d,v)    drv_set_field(lchip, t,f,d,(uint32*)(v))
#define DRV_GET_FIELD_V             drv_get_field32
#define DRV_GET_FIELD_A(lchip, t,f,d,v)    drv_get_field(lchip, t,f,d,(uint32*)(v))
#define DRV_SET_X_FIELD_A(lchip,w,s,b,d,v)    drv_set_x_field(lchip,w,s,b,d,(uint32*)v)
#define DRV_GET_X_FIELD_A(lchip,w,s,b,d,v)    drv_get_x_field(lchip,w,s,b,d,(uint32*)v)

#define DRV_SET_FLD_V2(lchip, tbl_id, field_name, entry, value, key_str, lkup_id)   \
    {\
        uint32 _fld_id_ = drv_usw_get_field_id_by_name(lchip, lkup_id, tbl_id, key_str, field_name);\
        if(0xFFFFFFFF != _fld_id_){\
        drv_set_field32(lchip, tbl_id, _fld_id_, (uint32*)(entry), value);\
        }\
    }
#define DRV_SET_FLD_A2(lchip, tbl_id, field_name, entry, value, key_str, lkup_id)   \
    {\
        uint32 _fld_id_ = drv_usw_get_field_id_by_name(lchip, lkup_id, tbl_id, key_str, field_name);\
        if(0xFFFFFFFF != _fld_id_){\
        drv_set_field(lchip, tbl_id, _fld_id_, entry, (uint32*)(value));\
        }\
    }
#define DRV_GET_FLD_V2(lchip, tbl_id, field_name, entry, value, key_str, lkup_id)   \
    {\
        uint32 _fld_id_ = drv_usw_get_field_id_by_name(lchip, lkup_id, tbl_id, key_str, field_name);\
        if(0xFFFFFFFF != _fld_id_){\
        value = drv_get_field32(lchip, tbl_id, _fld_id_, entry);\
        }\
    }
#define DRV_GET_FLD_A2(lchip, tbl_id, field_name, entry, value, key_str, lkup_id)   \
    {\
        uint32 _fld_id_ = drv_usw_get_field_id_by_name(lchip, lkup_id, tbl_id, key_str, field_name);\
        if(0xFFFFFFFF != _fld_id_){\
        drv_get_field(lchip, tbl_id, _fld_id_, entry, (uint32*)(value));\
        }\
    }

#define DRV_SET_FLD(X, T, f, ...)         DRV_SET_FIELD_ ## X(lchip, T ##_t, T ## _ ## f,  ##__VA_ARGS__)
#define DRV_GET_FLD(X, T, f, ...)        DRV_GET_FIELD_ ## X(lchip, T ##_t, T ## _ ## f,  ##__VA_ARGS__)
#define DRV_FLD_IS_EXISIT(tbl_id, field_id) \
    ( DRV_E_NONE == drv_field_support_check(lchip, tbl_id, field_id) )


#define DRV_TCAM_KEY_SIZE(lchip, tbl_id)  (uintptr)(drv_get_table_property_value(lchip, DRV_TABLE_PROP_TCAM_KEY_SIZE, tbl_id, 0))
#define DRV_TABLE_MAX_INDEX(lchip, tbl_id) (uintptr)(drv_get_table_property_value(lchip, DRV_TABLE_PROP_TABLE_MAX_IDX, tbl_id, 0))
#define DRV_TABLE_ENTRY_SIZE(lchip, tbl_id) (uintptr)(drv_get_table_property_value(lchip, DRV_TABLE_PROP_TABLE_ENTRY_SIZE, tbl_id, 0))
#define DRV_TABLE_DATA_BASE(lchip, tbl_id, index) (uintptr)(drv_get_table_property_value(lchip, DRV_TABLE_PROP_TABLE_DATA_BASE, tbl_id, index))
#define DRV_TCAM_START_INDEX(lchip, tbl_id, blk_id) (uintptr)(drv_get_table_property_value(lchip, DRV_TABLE_PROP_TCAM_START_SIZE, tbl_id, blk_id))
#define DRV_TABLE_NAME(lchip, tbl_id)   (char*)(drv_get_table_property_value(lchip, DRV_TABLE_PROP_TABLE_NAME, tbl_id, 0))



#define GET_ENUM_TYPE(start,end,value) drv_get_enum_type(lchip, start,end,value)

typedef struct {
        uint32 word_offset:  10;
        uint32 start:        8;
        uint32 bits:         14;
}segs_t;

typedef struct {
        uint32 field_id;
        uint32 bits:16;
        uint32 seg_num:16;
        segs_t *ptr_seg;
}fields_t;

typedef struct {
        char *ptr_field_name;
}fields_name_t;

/* Tcam data mask storage structure */
struct tbl_entry_s
{
    uint32* data_entry;
    uint32* mask_entry;
};
typedef struct tbl_entry_s tbl_entry_t;

enum drv_work_platform_type_e
{
    HW_PLATFORM = 0,
    SW_SIM_PLATFORM = 1,
    MAX_WORK_PLATFORM = 2,
};
typedef enum drv_work_platform_type_e drv_work_platform_type_t;

enum drv_access_type_e
{
    DRV_PCI_ACCESS,
    DRV_I2C_ACCESS,

    DRV_MAX_ACCESS_TYPE
};
typedef enum drv_access_type_e drv_access_type_t;

/**
 @brief define the byte order
*/
enum host_type_e
{
    HOST_LE = 0,     /**< little edian */
    HOST_BE = 1,     /**< big edian */
};
typedef enum host_type_e host_type_t;

enum drv_table_property_e
{
    DRV_TABLE_PROP_TYPE,
    DRV_TABLE_PROP_HW_ADDR,
    DRV_TABLE_PROP_GET_NAME,
    DRV_TABLE_PROP_BITMAP,
    DRV_TABLE_PROP_FIELD_NUM,
    DRV_TABLE_PROP_TCAM_KEY_SIZE,
    DRV_TABLE_PROP_TCAM_START_SIZE,
    DRV_TABLE_PROP_TABLE_MAX_IDX,
    DRV_TABLE_PROP_TABLE_ENTRY_SIZE,
    DRV_TABLE_PROP_TABLE_DATA_BASE,
    DRV_TABLE_PROP_TABLE_NAME,
    DRV_TABLE_PROP_SDB_INFO,
    DRV_TABLE_PROP_FIELD_INFO,

    MAX_DRV_TABLE_PROP
};
typedef enum drv_table_property_e drv_table_property_t;

/* table extended property type */
enum drv_table_type_s
{
    DRV_TABLE_TYPE_NORMAL = 0,
    DRV_TABLE_TYPE_TCAM,
    DRV_TABLE_TYPE_TCAM_AD,
    DRV_TABLE_TYPE_TCAM_LPM_AD,
    DRV_TABLE_TYPE_TCAM_NAT_AD,
    DRV_TABLE_TYPE_LPM_TCAM_IP,
    DRV_TABLE_TYPE_LPM_TCAM_NAT,
    DRV_TABLE_TYPE_STATIC_TCAM_KEY,
    DRV_TABLE_TYPE_DESC,
    DRV_TABLE_TYPE_DBG,
    DRV_TABLE_TYPE_DYNAMIC,
    DRV_TABLE_TYPE_MIXED,
    DRV_TABLE_TYPE_INVALID,
};
typedef enum drv_table_type_s drv_table_type_t;

#if defined (TSINGMA_MX) || defined (TSINGMA_GX) || defined (ARCTIC)
struct drv_io_callback_fun_s
{
    int32(*drv_sram_tbl_read)(uint8, tbls_id_t, uint32, uint32*);
    int32(*drv_sram_tbl_write)(uint8, tbls_id_t, uint32, uint32*);
    int32(*drv_tcam_tbl_read)(uint8, tbls_id_t, uint32, tbl_entry_t*);
    int32(*drv_tcam_tbl_write)(uint8, tbls_id_t, uint32, tbl_entry_t*);
    int32(*drv_tcam_tbl_remove)(uint8, tbls_id_t, uint32);
};
typedef struct drv_io_callback_fun_s drv_io_callback_fun_t;
#else
struct drv_io_callback_fun_s
{
    int32(*drv_sram_tbl_read)(uint8, uint32, uint32, uint8 , uint32*);
    int32(*drv_sram_tbl_write)(uint8, uint32, uint32, uint8 , uint32*);
    int32(*drv_tcam_tbl_read)(uint8, uint32, uint32, uint8 , uint32*);
    int32(*drv_tcam_tbl_write)(uint8, uint32, uint32, uint8 , uint32*);
    int32(*drv_tcam_tbl_remove)(uint8, uint32, uint32, uint8 , uint32*);
};
typedef struct drv_io_callback_fun_s drv_io_callback_fun_t;
#endif


enum drv_chip_series_e
{
    DRV_DUET2,
    DRV_TSINGMA,
    DRV_TSINGMA_MX,
    DRV_TSINGMA_GX,
    DRV_ARCTIC,
    MAX_DRV_CHIP,
};
typedef enum drv_chip_series_e drv_chip_series_t;

typedef struct drv_master_s drv_master_t;

#define ________ACC_________
enum drv_acc_flag_e
{
    DRV_ACC_ENTRY_DYNAMIC,
    DRV_ACC_ENTRY_STATIC,
    DRV_ACC_UPDATE_MAC_LIMIT_CNT,             /* for port/vlan/dynamic mac limit*/
    DRV_ACC_STATIC_MAC_LIMIT_CNT,             /* static fdb do mac limit */
    DRC_ACC_PROFILE_MAC_LIMIT_EN,             /* profile mac limit  */
    DRV_ACC_AGING_EN,                         /* used for add fdb by key */
    DRV_ACC_OVERWRITE_EN,                     /* used for add fdb by key and mac limit*/
    DRV_ACC_MAC_LIMIT_NEGATIVE,               /* used for update mac limit count */
    DRV_ACC_MAC_LIMIT_STATUS,                 /* used for update mac limit status */
    DRV_ACC_USE_LOGIC_PORT,
    DRV_ACC_ENTRY_UCAST,                      /* used for dump ucast entry */
    DRV_ACC_ENTRY_MCAST,                      /* used for dump mcast entry */
    DRV_ACC_ENTRY_PENDING,                    /* used for dump pending entry */
    DRV_ACC_FORCE_STORE_SDB,                  /* used for l2mc & ip based l2mc hw reset */
    DRV_ACC_ENTRY_LOCAL_DYNAMIC,              /* used for dump and flush local dynamic fdb */
    DRV_ACC_MAX_FLAG
};
typedef enum drv_acc_flag_e drv_acc_flag_t;

enum drv_acc_op_type_e
{
    DRV_ACC_OP_BY_INDEX = 0x1,     /* used for acc add/del/lookup by index */
    DRV_ACC_OP_BY_KEY = 0x2,       /* used for acc add/del/lookup by key */
    DRV_ACC_OP_BY_MAC = 0x4,       /* used for dump/flush */
    DRV_ACC_OP_BY_PORT = 0x8,      /* used for dump/flush */
    DRV_ACC_OP_BY_VLAN = 0x10,      /* used for dump/flush */
    DRV_ACC_OP_BY_ALL = 0x20,       /* used for dump/flush */

    DRV_ACC_FLAG_NUM
};
typedef enum drv_acc_op_type_e drv_acc_op_type_t;

enum drv_acc_type_e
{
    DRV_ACC_TYPE_ADD,               /* Add key action for all acc type */
    DRV_ACC_TYPE_DEL,               /* Del key action for all acc type */
    DRV_ACC_TYPE_LOOKUP,            /* Lookup key action for all acc type */
    DRV_ACC_TYPE_DUMP,              /* dump key action for FDB acc type */
    DRV_ACC_TYPE_FLUSH,             /* Flush key action for FDB acc type */
    DRV_ACC_TYPE_ALLOC,             /* used only for userid/xcoam/flowhash */
    DRV_ACC_TYPE_UPDATE,
    DRV_ACC_TYPE_CALC,              /* Calculate key index for all acc type */
    DRV_ACC_TYPE_DUMP_FLEX,    /* dump key action for FDB acc type by match data and mask */
    DRV_ACC_TYPE_FLUSH_FLEX,   /* Flush key action for FDB acc type by match data and mask */
    DRV_ACC_TYPE_FLUSH_CACHE, /* Flush cache for FDB acc type */
    DRV_ACC_MAX_TYPE
};
typedef enum drv_acc_type_e drv_acc_type_t;

enum drv_acc_hash_module_e
{
    DRV_ACC_HASH_MODULE_FDB,
    DRV_ACC_HASH_MODULE_FIB_HOST0,
    DRV_ACC_HASH_MODULE_FIB_HOST1,
    DRV_ACC_HASH_MODULE_EGRESS_XC,
    DRV_ACC_HASH_MODULE_FLOW,
    DRV_ACC_HASH_MODULE_USERID,
    DRV_ACC_HASH_MODULE_EGRESS_SCL,
    DRV_ACC_HASH_MODULE_OAM, /*TMM*/
    DRV_ACC_HASH_MODULE_RMEP, /*TMM*/
    DRV_ACC_HASH_MODULE_MAC_LIMIT,
    DRV_ACC_HASH_MODULE_IPFIX,
    DRV_ACC_HASH_MODULE_CID,
    DRV_ACC_HASH_MODULE_AGING,
    DRV_ACC_HASH_MODULE_FIB_HASH, /*TM*/
    DRV_ACC_HASH_MODULE_MPLS_HASH, /*TM*/
    DRV_ACC_HASH_MODULE_GEMPORT_HASH, /*TM*/
    DRV_ACC_HASH_MODULE_QUEUE_MAP_HASH, /*TMM*/
    DRV_ACC_HASH_MODULE_IPL2MC,
    DRV_ACC_HASH_MODULE_DOT1AE,/*AT*/
    DRV_ACC_HASH_MODULE_X_FLOW,/*AT*/
    DRV_ACC_HASH_MODULE_NUM,
};
typedef enum drv_acc_hash_module_e drv_acc_hash_module_t;

struct drv_acc_in_s
{
    uint32     tbl_id;          /* acc operation table id */
    uint8       type;            /* refer to drv_acc_type_t */
    uint8       op_type;         /* refer to drv_acc_op_type_t */
    uint8       dir;             /* for ipfix ingress/egres*/
    uint8       level;
    uint32      flag;           /* refer to drv_acc_flag_t */
    uint32      index;          /* for op_type=DRV_ACC_OP_BY_INDEX means key index, for dump means start index */
    uint32      query_end_index;/* dump end key index and this key is excluded */
    uint32      query_cnt;      /* dump using, max number for one query */
    uint16      gport;
    uint8       timer_index;    /* used for add fdb by key */
    uint8       offset;         /* used for cid acc, only add by index will use, indicate bucket offset*/
    uint32      limit_cnt;      /* increase/decrease number or new count,
                                   if DRV_ACC_MAC_LIMIT_STATUS is set, means status: discard or not discard*/
    uint8      module;
    uint8 oper_bmp; /* only for chip from AT, means operation on the specific slice */
    void*       data;
    uint32     value;
    uint8      dp_id;
};
typedef struct drv_acc_in_s drv_acc_in_t;

struct drv_acc_out_s
{
    uint32      key_index;      /* by index */
    uint32      ad_index;       /* only used for lookup by key */

    uint8       is_full;        /* for add by key and mac limit means reach mac limit threshold,
                                   for dump means dma full*/
    uint8       is_conflict;
    uint8       is_hit;
    uint8       is_pending;

    uint8       is_end;
    uint8       is_left;        /*only used for cid acc*/
    uint8       offset;         /*only used for cid acc*/
    uint8       tcam_hit;

    uint32      query_cnt;
    uint32      data[40]; /*10*4*/
    uint8       out_level[40];  /*only used for get calc key index, return associated level*/
};
typedef struct drv_acc_out_s drv_acc_out_t;

#define ________ECC__________
struct drv_ecc_intr_tbl_s
{
    uint32              intr_tblid  : 15;
    uint32              intr_bit    : 8;
    uint32              intr_fld    : 9;

    uint32              action      : 2;
    uint32              err_type    : 3;
    uint32              rec_id      : 15;
    uint32              rec_id_fld  : 12;

    uint32              mem_id      : 15;
    uint32              tbl_type    : 3;
    uint32              rsv         : 14;
};
typedef struct drv_ecc_intr_tbl_s drv_ecc_intr_tbl_t;

enum drv_ecc_scan_type_e
{
    DRV_ECC_SCAN_TYPE_TCAM,
    DRV_ECC_SCAN_TYPE_SBE,
    DRV_ECC_SCAN_TYPE_NUM
};
typedef enum drv_ecc_scan_type_e drv_ecc_scan_type_t;

struct drv_ecc_intr_param_s
{
    uint32     intr_tblid;       /**< interrupt tbl id */
    uint32*    p_bmp;            /**< bitmap of interrupt status */
    uint16     total_bit_num;    /**< total bit num */
    uint16     valid_bit_count;  /**< valid bit count */
    void*      intr_type;        /**< interrupt type */
};
typedef struct drv_ecc_intr_param_s drv_ecc_intr_param_t;

enum drv_ftm_mem_id_e
{
    DRV_FTM_SRAM0,
    DRV_FTM_SRAM1,

    DRV_FTM_SRAM2,
    DRV_FTM_SRAM3,
    DRV_FTM_SRAM4,
    DRV_FTM_SRAM5,
    DRV_FTM_SRAM6,
    DRV_FTM_SRAM7,
    DRV_FTM_SRAM8,

    DRV_FTM_SRAM9,
    DRV_FTM_SRAM10,
    DRV_FTM_SRAM11,
    DRV_FTM_SRAM12,
    DRV_FTM_SRAM13,
    DRV_FTM_SRAM14,
    DRV_FTM_SRAM15,
    DRV_FTM_SRAM16,
    DRV_FTM_SRAM17,
    DRV_FTM_SRAM18,
    DRV_FTM_SRAM19,

    DRV_FTM_SRAM20,
    DRV_FTM_SRAM21,
    DRV_FTM_SRAM22,
    DRV_FTM_SRAM23,
    DRV_FTM_SRAM24,
    DRV_FTM_SRAM25,
    DRV_FTM_SRAM26,

    DRV_FTM_SRAM27,
    DRV_FTM_SRAM28,
    DRV_FTM_SRAM29,
    DRV_FTM_SRAM30,
    DRV_FTM_SRAM31,
    DRV_FTM_SRAM32,

    DRV_FTM_SRAM33,
    DRV_FTM_SRAM34,
    DRV_FTM_SRAM35,
    DRV_FTM_SRAM36,
    DRV_FTM_SRAM37,
    DRV_FTM_SRAM38,
    DRV_FTM_SRAM39,

    DRV_FTM_SRAM40,
    DRV_FTM_SRAM41,
    DRV_FTM_SRAM42,

    DRV_FTM_SRAM43,
    DRV_FTM_SRAM44,
    DRV_FTM_SRAM45,

    DRV_FTM_SRAM46,
    DRV_FTM_SRAM47,
    DRV_FTM_SRAM48,
    DRV_FTM_SRAM49,
    DRV_FTM_SRAM50,
    DRV_FTM_SRAM51,
    DRV_FTM_SRAM52,
    DRV_FTM_SRAM53,
    DRV_FTM_SRAM54,

    DRV_FTM_SRAM_MAX,
    DRV_FTM_MIXED0,
    DRV_FTM_MIXED1,
    DRV_FTM_MIXED2,
    DRV_FTM_EDRAM_MAX,

    DRV_FTM_TCAM_KEY0,
    DRV_FTM_TCAM_KEY1,
    DRV_FTM_TCAM_KEY2,
    DRV_FTM_TCAM_KEY3,

    DRV_FTM_TCAM_KEY4,
    DRV_FTM_TCAM_KEY5,
    DRV_FTM_TCAM_KEY6,
    DRV_FTM_TCAM_KEY7,
    DRV_FTM_TCAM_KEY8,
    DRV_FTM_TCAM_KEY9,
    DRV_FTM_TCAM_KEY10,
    DRV_FTM_TCAM_KEY11,
    DRV_FTM_TCAM_KEY12,
    DRV_FTM_TCAM_KEY13,
    DRV_FTM_TCAM_KEY14,
    DRV_FTM_TCAM_KEY15,
    DRV_FTM_TCAM_KEY16,
    DRV_FTM_TCAM_KEY17,
    DRV_FTM_TCAM_KEY18,
    DRV_FTM_TCAM_KEY19,

    DRV_FTM_TCAM_KEY20,
    DRV_FTM_TCAM_KEY21,
    DRV_FTM_TCAM_KEY22,
    DRV_FTM_TCAM_KEY23,

    DRV_FTM_TCAM_KEY24,
    DRV_FTM_TCAM_KEY25,
    DRV_FTM_TCAM_KEY26,
    DRV_FTM_TCAM_KEY27,
    DRV_FTM_TCAM_KEY28,
    DRV_FTM_TCAM_KEY29,
    DRV_FTM_TCAM_KEY30,
    DRV_FTM_TCAM_KEY31,
    DRV_FTM_TCAM_KEY32,
    DRV_FTM_TCAM_KEY33,
    DRV_FTM_TCAM_KEY34,
    DRV_FTM_TCAM_KEY35,
    DRV_FTM_TCAM_KEY36,
    DRV_FTM_TCAM_KEY37,
    DRV_FTM_TCAM_KEY38,
    DRV_FTM_TCAM_KEY39,
    DRV_FTM_TCAM_KEY40,
    DRV_FTM_TCAM_KEY41,

    DRV_FTM_TCAM_KEYM,

    DRV_FTM_TCAM_AD0,
    DRV_FTM_TCAM_AD1,
    DRV_FTM_TCAM_AD2,
    DRV_FTM_TCAM_AD3,
    DRV_FTM_TCAM_AD4,
    DRV_FTM_TCAM_AD5,
    DRV_FTM_TCAM_AD6,
    DRV_FTM_TCAM_AD7,
    DRV_FTM_TCAM_AD8,
    DRV_FTM_TCAM_AD9,
    DRV_FTM_TCAM_AD10,
    DRV_FTM_TCAM_AD11,
    DRV_FTM_TCAM_AD12,
    DRV_FTM_TCAM_AD13,
    DRV_FTM_TCAM_AD14,
    DRV_FTM_TCAM_AD15,
    DRV_FTM_TCAM_AD16,
    DRV_FTM_TCAM_AD17,
    DRV_FTM_TCAM_AD18,
    DRV_FTM_TCAM_AD19,
    DRV_FTM_TCAM_AD20,
    DRV_FTM_TCAM_AD21,
    DRV_FTM_TCAM_AD22,   /*100*/
    DRV_FTM_TCAM_AD23,
    DRV_FTM_TCAM_AD24,
    DRV_FTM_TCAM_AD25,
    DRV_FTM_TCAM_AD26,
    DRV_FTM_TCAM_AD27,
    DRV_FTM_TCAM_AD28,
    DRV_FTM_TCAM_AD29,
    DRV_FTM_TCAM_AD30,
    DRV_FTM_TCAM_AD31,
    DRV_FTM_TCAM_AD32,
    DRV_FTM_TCAM_AD33,
    DRV_FTM_TCAM_AD34,
    DRV_FTM_TCAM_AD35,
    DRV_FTM_TCAM_AD36,
    DRV_FTM_TCAM_AD37,
    DRV_FTM_TCAM_AD38,
    DRV_FTM_TCAM_AD39,
    DRV_FTM_TCAM_AD40,
    DRV_FTM_TCAM_AD41,

    DRV_FTM_TCAM_ADM,

    DRV_FTM_LPM_TCAM_KEY0,
    DRV_FTM_LPM_TCAM_KEY1,
    DRV_FTM_LPM_TCAM_KEY2,
    DRV_FTM_LPM_TCAM_KEY3,
    DRV_FTM_LPM_TCAM_KEY4,
    DRV_FTM_LPM_TCAM_KEY5,
    DRV_FTM_LPM_TCAM_KEY6,
    DRV_FTM_LPM_TCAM_KEY7,
    DRV_FTM_LPM_TCAM_KEY8,
    DRV_FTM_LPM_TCAM_KEY9,
    DRV_FTM_LPM_TCAM_KEY10,
    DRV_FTM_LPM_TCAM_KEY11,
    DRV_FTM_LPM_TCAM_KEYM,

    DRV_FTM_LPM_TCAM_AD0,
    DRV_FTM_LPM_TCAM_AD1,
    DRV_FTM_LPM_TCAM_AD2,
    DRV_FTM_LPM_TCAM_AD3,
    DRV_FTM_LPM_TCAM_AD4,
    DRV_FTM_LPM_TCAM_AD5,
    DRV_FTM_LPM_TCAM_AD6,
    DRV_FTM_LPM_TCAM_AD7,
    DRV_FTM_LPM_TCAM_AD8,
    DRV_FTM_LPM_TCAM_AD9,
    DRV_FTM_LPM_TCAM_AD10,
    DRV_FTM_LPM_TCAM_AD11,

    DRV_FTM_LPM_TCAM_ADM,

    /*static tcam key*/
    DRV_FTM_QUEUE_TCAM,/*only for TM.D2*/
    DRV_FTM_CID_TCAM,
    DRV_FTM_SEL_TCAM,
    DRV_FTM_SEL_TCAM_EGR,
    DRV_FTM_RMAC_TCAM,
    DRV_FTM_UDF_TCAM,

    DRV_FTM_MAX_ID
};
typedef enum drv_ftm_mem_id_e drv_ftm_mem_id_t;

enum drv_ftm_sram_tbl_type_e
{
    DRV_FTM_SRAM_TBL_MAC_HASH_KEY,
    DRV_FTM_SRAM_TBL_FIB0_HASH_KEY,
    DRV_FTM_SRAM_TBL_FIB1_HASH_KEY,
    DRV_FTM_SRAM_TBL_FLOW_HASH_KEY,
    DRV_FTM_SRAM_TBL_IPFIX_HASH_KEY,
    DRV_FTM_SRAM_TBL_IPFIX_HASH_KEY1,
    DRV_FTM_SRAM_TBL_USERID_HASH_KEY,
    DRV_FTM_SRAM_TBL_USERID1_HASH_KEY,
    DRV_FTM_SRAM_TBL_XCOAM_HASH_KEY,
    DRV_FTM_SRAM_TBL_EGRSCL0_HASH_KEY,
    DRV_FTM_SRAM_TBL_EGRSCL1_HASH_KEY,

    DRV_FTM_SRAM_TBL_LPM_LKP_KEY0,
    DRV_FTM_SRAM_TBL_LPM_LKP_KEY1,

    DRV_FTM_SRAM_TBL_LPM_LKP_KEY2,
    DRV_FTM_SRAM_TBL_LPM_LKP_KEY3,

    DRV_FTM_SRAM_TBL_DSMAC_AD,
    DRV_FTM_SRAM_TBL_DSIP_AD,
    DRV_FTM_SRAM_TBL_FLOW_AD,
    DRV_FTM_SRAM_TBL_IPFIX_AD,
    DRV_FTM_SRAM_TBL_IPFIX_AD1,
    DRV_FTM_SRAM_TBL_USERID_AD,
    DRV_FTM_SRAM_TBL_USERID_AD1,

    DRV_FTM_SRAM_TBL_NEXTHOP,
    DRV_FTM_SRAM_TBL_FWD,
    DRV_FTM_SRAM_TBL_MET,
    DRV_FTM_SRAM_TBL_EDIT,

    DRV_FTM_SRAM_TBL_OAM_APS,
    DRV_FTM_SRAM_TBL_OAM_LM,
    DRV_FTM_SRAM_TBL_OAM_PROTOCOL_LM,
    DRV_FTM_SRAM_TBL_OAM_MEP,
    DRV_FTM_SRAM_TBL_OAM_MA,
    DRV_FTM_SRAM_TBL_OAM_MA_NAME,

    DRV_FTM_SRAM_TBL_MPLS_HASH_KEY,
    DRV_FTM_SRAM_TBL_MPLS_HASH_AD,

    DRV_FTM_SRAM_TBL_GEM_PORT,


    DRV_FTM_SRAM_TBL_OAM_RMEP_KEY,
    DRV_FTM_SRAM_TBL_OAM_HASH_KEY,
    DRV_FTM_SRAM_TBL_ANT_FLOW,
    DRV_FTM_SRAM_TBL_ANT_FLOW2, /*used for ecmp*/
    DRV_FTM_SRAM_TBL_QUEUE_HASH_KEY,

    DRV_FTM_SRAM_TBL_NHOFST_MAP,
    DRV_FTM_SRAM_TBL_FWD2,
    DRV_FTM_SRAM_TBL_EDIT_OUTER,
    DRV_FTM_SRAM_TBL_EDIT2, /* X-Edit */
    DRV_FTM_SRAM_TBL_MET2, /* ShareMet */
    DRV_FTM_SRAM_TBL_XKEY, /* X-Key1 */
    DRV_FTM_SRAM_TBL_XKEY2, /* X-Key2 */
    DRV_FTM_SRAM_TBL_XSEC_RX,
    DRV_FTM_SRAM_TBL_XSEC_TX,

    DRV_FTM_SRAM_TBL_MAX
};
typedef enum drv_ftm_sram_tbl_type_e drv_ftm_sram_tbl_type_t;


#define DRV_FTM_FTM_MAX_EDRAM_MEM_NUM       20
#define DRV_FTM_FTM_MAX_TCAM_TBL_NUM        22

enum drv_ftm_tcam_key_type_e
{
    DRV_FTM_TCAM_TYPE_IGS_ACL0,
    DRV_FTM_TCAM_TYPE_IGS_ACL1,
    DRV_FTM_TCAM_TYPE_IGS_ACL2,
    DRV_FTM_TCAM_TYPE_IGS_ACL3,
    DRV_FTM_TCAM_TYPE_IGS_ACL4,
    DRV_FTM_TCAM_TYPE_IGS_ACL5,
    DRV_FTM_TCAM_TYPE_IGS_ACL6,
    DRV_FTM_TCAM_TYPE_IGS_ACL7,
    DRV_FTM_TCAM_TYPE_IGS_ACL8,
    DRV_FTM_TCAM_TYPE_IGS_ACL9,
    DRV_FTM_TCAM_TYPE_IGS_ACL10,
    DRV_FTM_TCAM_TYPE_IGS_ACL11,
    DRV_FTM_TCAM_TYPE_IGS_ACL12,
    DRV_FTM_TCAM_TYPE_IGS_ACL13,
    DRV_FTM_TCAM_TYPE_IGS_ACL14,
    DRV_FTM_TCAM_TYPE_IGS_ACL15,
    DRV_FTM_TCAM_TYPE_IGS_ACL16,
    DRV_FTM_TCAM_TYPE_IGS_ACL17,
    DRV_FTM_TCAM_TYPE_IGS_ACL18,
    DRV_FTM_TCAM_TYPE_IGS_ACL19,
    DRV_FTM_TCAM_TYPE_IGS_ACL20,
    DRV_FTM_TCAM_TYPE_IGS_ACL21,
    DRV_FTM_TCAM_TYPE_IGS_ACL22,
    DRV_FTM_TCAM_TYPE_IGS_ACL23,

    DRV_FTM_TCAM_TYPE_EGS_ACL0,
    DRV_FTM_TCAM_TYPE_EGS_ACL1,
    DRV_FTM_TCAM_TYPE_EGS_ACL2,
    DRV_FTM_TCAM_TYPE_EGS_ACL3,
    DRV_FTM_TCAM_TYPE_EGS_ACL4,
    DRV_FTM_TCAM_TYPE_EGS_ACL5,
    DRV_FTM_TCAM_TYPE_EGS_ACL6,
    DRV_FTM_TCAM_TYPE_EGS_ACL7,
    DRV_FTM_TCAM_TYPE_EGS_ACL8,
    DRV_FTM_TCAM_TYPE_EGS_ACL9,
    DRV_FTM_TCAM_TYPE_EGS_ACL10,
    DRV_FTM_TCAM_TYPE_EGS_ACL11,

    DRV_FTM_TCAM_TYPE_IGS_USERID0,
    DRV_FTM_TCAM_TYPE_IGS_USERID1,
    DRV_FTM_TCAM_TYPE_IGS_USERID2,
    DRV_FTM_TCAM_TYPE_IGS_USERID3,

    DRV_FTM_TCAM_TYPE_EGS_SCL0,
    DRV_FTM_TCAM_TYPE_EGS_SCL1,

    DRV_FTM_TCAM_TYPE_IGS_LPM_ALL,          /* just for cmode use 13*/

     /*can not change start*/
    DRV_FTM_TCAM_TYPE_IGS_LPM0DA,           /* private ipda */
    DRV_FTM_TCAM_TYPE_IGS_LPM0SA,           /* private ipsa */
    DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB,        /* public ipda, include lookup1 & lookup 2 */
    DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB,        /* public ipsa include lookup1 & lookup 2 */
#if 0
    DRV_FTM_TCAM_TYPE_IGS_LPM0DA_V6_HALF,
    DRV_FTM_TCAM_TYPE_IGS_LPM0SA_V6_HALF,           /* private ipsa */
    DRV_FTM_TCAM_TYPE_IGS_LPM0DAPUB_V6_HALF,        /* public ipda, include*/
    DRV_FTM_TCAM_TYPE_IGS_LPM0SAPUB_V6_HALF,        /* public ipsa include*/
#endif

    DRV_FTM_TCAM_TYPE_IGS_LPM1,

     /*can not change end*/
    DRV_FTM_TCAM_TYPE_STATIC_TCAM,

    DRV_FTM_KEY_TYPE_IPV4_UCAST,
    DRV_FTM_KEY_TYPE_IPV4_NAT,
    DRV_FTM_KEY_TYPE_IPV6_UCAST,
    DRV_FTM_KEY_TYPE_IPV6_UCAST_HALF,

    DRV_FTM_TCAM_TYPE_MAX
};
typedef enum drv_ftm_tcam_key_type_e drv_ftm_tcam_key_type_t;

//Cmodel Modify
enum drv_ftm_module_s
{
    TCAM_MODULE_NONE,
    TCAM_MODULE_IGR_SCL0,
    TCAM_MODULE_IGR_SCL1,
    TCAM_MODULE_IGR_ACL,
    TCAM_MODULE_EGR_ACL,
    TCAM_MODULE_EGR_SCL,
    TCAM_MODULE_LPM,
    TCAM_MODULE_SCL, /*D2 and TM used*/
    TCAM_MODULE_ACL, /*D2 and TM used*/
    TCAM_MODULE_NUM
};

/*
{
    TCAM_MODULE_NONE = 0,
    TCAM_MODULE_IGR_ACL = 1,
    TCAM_MODULE_EGR_ACL = 2,
    TCAM_MODULE_IGR_SCL0,
    TCAM_MODULE_IGR_SCL1,
    TCAM_MODULE_EGR_SCL,

    TCAM_MODULE_ACL ,
    TCAM_MODULE_SCL,


    TCAM_MODULE_LPM,
    TCAM_MODULE_NUM
};
*/
enum drv_ftm_info_type_e
{
    DRV_FTM_INFO_TYPE_CAM,
    DRV_FTM_INFO_TYPE_TCAM,
    DRV_FTM_INFO_TYPE_EDRAM,
    DRV_FTM_INFO_TYPE_LPM_MODEL,        /* ftm lpm model */
    DRV_FTM_INFO_TYPE_NAT_PBR_EN,       /* ftm nat/pbr enable */
    DRV_FTM_INFO_TYPE_LPM_TCAM_INIT_SIZE,
    DRV_FTM_INFO_TYPE_LPM_TCAM_INIT_BMP,
    DRV_FTM_INFO_TYPE_PIPELINE_INFO,
    DRV_FTM_INFO_TYPE_SCL_MODE,
    DRV_FTM_INFO_TYPE_MAX,
};
typedef enum drv_ftm_info_type_e drv_ftm_info_type_t;

struct drv_ftm_info_detail_s
{
    uint8 info_type;                /*< [GG]drv_ftm_info_type_t */
    uint8 tbl_type;                 /*< [GG]drv_ftm_key_type_t or drv_ftm_tbl_type_t or drv_ftm_cam_type_t*/
    uint8 tbl_entry_num;
    uint8 op;        /*0: all; 1: only get tbl_entry_num*/

    /*for edram*/
    uint8 mem_id[DRV_FTM_FTM_MAX_EDRAM_MEM_NUM];
    uint32 entry_num[DRV_FTM_FTM_MAX_EDRAM_MEM_NUM];
    uint32 offset[DRV_FTM_FTM_MAX_EDRAM_MEM_NUM];

    /*for tcam*/
    uint32 tbl_id[DRV_FTM_FTM_MAX_TCAM_TBL_NUM];
    uint32 key_size[DRV_FTM_FTM_MAX_TCAM_TBL_NUM];
    uint32 max_idx[DRV_FTM_FTM_MAX_TCAM_TBL_NUM];

    /* for cam */
    uint8 max_size;
    uint8 used_size;
    uint8 scl_mode;
    uint8 nsh_mode;

    union {
        uint32 lpm_model;
        uint32 nat_pbr_en;
        uint32 lpm_tcam_init_size[2][3];//0 private, 1 public; 0: ipv6 full, 1: ipv6 half, 2: ipv4 boundary
        uint32 lpm_tcam_init_bmp[2][3];
        struct
        {
            uint32 size0;
            uint32 size1;
        }pipeline_info;
    }l3;


    char str[64];
};
typedef struct drv_ftm_info_detail_s drv_ftm_info_detail_t;

enum drv_ftm_mem_info_type_e
{
    DRV_FTM_MEM_INFO_MEM_TYPE,
    DRV_FTM_MEM_INFO_MEM_TYPE_DETAIL,
    DRV_FTM_MEM_INFO_ENTRY_ENUM,
    DRV_FTM_MEM_INFO_TBL_INDEX,
};
typedef enum drv_ftm_mem_info_type_e drv_ftm_mem_info_type_t;

struct drv_ftm_mem_info_s
{
    uint8 info_type;                /*< drv_ftm_mem_info_type_t */
    uint32 mem_id;
    uint32 mem_offset;

    uint8 mem_type;
    uint8 mem_sub_id;

    uint32 entry_num;

    uint32 table_id;
    uint32 index;
};
typedef struct drv_ftm_mem_info_s drv_ftm_mem_info_t;

struct drv_ftm_tcam_info_s
{
    uint32 tcam_mem_id;
    uint32 entry_offset;
    uintptr sw_addr;
};
typedef struct drv_ftm_tcam_info_s drv_ftm_tcam_info_t;

struct drv_mchip_ftm_s
{
    int32 (*ftm_set_hash_poly)(uint8 lchip, uint32 mem_id, uint8 sram_type, uint32 drv_poly);
    int32 (*ftm_get_hash_poly)(uint8 lchip, uint32 mem_id, uint8 sram_type, uint32* drv_poly);
    int32 (*ftm_lookup_ctl_init)(uint8 lchip);
    int32 (*ftm_mem_alloc)(uint8 lchip, void* p_profile_info);
    int32 (*ftm_mem_free)(uint8 lchip);
    int32 (*ftm_get_info_detail)(uint8 lchip, drv_ftm_info_detail_t* p_ftm_info);
    int32 (*ftm_get_sram_type)(uint8 lchip, uint32 mem_id, uint8* p_sram_type);
    int32 (*ftm_get_mem_info)(uint8 lchip, drv_ftm_mem_info_t* p_mem_info);
    int32 (*ftm_table_id_2_mem_id)(uint8 lchip, uint32 tbl_id, uint32 tbl_idx, uint32* p_mem_id, uint32* p_offset);
    int32 (*ftm_get_memory_size)(uint8 lchip, uint32 mem_id, uint32*p_mem_size);
    int32 (*ftm_get_cam_by_tbl_id)(uint8 lchip, uint32 tbl_id, uint8* cam_type, uint8* cam_num);
    int32 (*ftm_set_misc_config)(uint8 lchip);
    int32 (*ftm_adjust_flow_tcam)(uint8 lchip, uint8 expand_key, uint8 compress_key);
    int32 (*ftm_adjust_mac_table)(uint8 lchip, void* p_profile);
    int32 (*ftm_reset_tcam_table)(uint8 lchip);

    int32 (*ftm_set_dynamic_ram_couple_mode)(uint8 lchip, uint32 couple_mode);
    int32 (*ftm_get_dynamic_ram_couple_mode)(uint8 lchip, uint16 sram_type, uint32* couple_mode);
    int32 (*ftm_get_tcam_tbl_info_detail)(uint8 lchip, char* p_tbl_name);
    int32 (*ftm_get_tcam_memory_info)(uint8 lchip, uint32 mem_id, uint32* p_mem_addr, uint32* p_entry_num, uint32* p_entry_size, void* tcam_info);
    uint32 (*ftm_memid_2_table)(uint8 lchip, uint32 mem_id);
    int32 (*ftm_get_mplshash_mode)(uint8 lchip, uint8* is_mpls);
    int32 (*ftm_get_flow_stats_table_id)(uint8 lchip, uint8 ram_idx, uint32* table_id);
    uint8 (*ftm_sram_get_sdb_en)(uint8 lchip, uint8 ram_id);
    int32 (*ftm_get_ram_with_chip_op)(uint8 lchip, uint8 ram_id);
    int32 (*ftm_reset_dynamic_table)(uint8 lchip);
    int32 (*ftm_alloc_tcam)(uint8 lchip, uint8 start_key_type, uint8 end_key_type, uint8 force_realloc);
    int32 (*ftm_mapping_drv_hash_poly_type)(uint8 lchip, uint8 sram_type, uint32 type, uint32* p_poly);
    int32 (*ftm_get_current_hash_poly_type)(uint8 lchip, uint32 mem_id, uint8 sram_type, uint32 *poly_type);
    int32 (*ftm_get_hash_poly_cap)(uint8 lchip, uint8 sram_type, uint32 mem_id, uint8* poly_num, uint32* poly_type);
    int32 (*ftm_show_hash_poly)(uint8 lchip, uint32 mem_id, uint8 sram_type);
    int32 (*ftm_get_sram_tbl_id)(uint8 lchip, uint32 sram_type, uint32* p_sram_tbl_id, uint8* p_share_num, uint8* p_per_tbl_entry_num);
};
typedef struct drv_mchip_ftm_s drv_mchip_ftm_t;

struct drv_mchip_ser_s
{
    int32 (*ser_get_mem_desc_index)(uint8 lchip, uint32 mem_id, uint32* p_desc_index);
    int32 (*ser_dma_recover_tcam)(uint8 lchip, void* p_param);
};
typedef struct drv_mchip_ser_s drv_mchip_ser_t;

struct drv_mchip_sdb_s
{
    int32 (*drv_sdb_write_api)(uint8 lchip, tbls_id_t tbl_id, uint32 entry_idx, void* p_data, uint32 entry_size, uint8 oper_bmp);
};
typedef struct drv_mchip_sdb_s drv_mchip_sdb_t;

struct drv_mchip_api_s
{
    drv_mchip_ftm_t *p_mchip_ftm;
    drv_mchip_ser_t *p_mchip_ser;
    drv_mchip_sdb_t *p_mchip_sdb;
};
typedef struct drv_mchip_api_s drv_mchip_api_t;

/*this struct should be same with sys_dma_tbl_rw_t*/
struct drv_dma_tbl_rw_s
{
    uint32* buffer;
    uint32  tbl_addr;

    uint32  entry_num;
    uint32  entry_len;

    uint32  is_pause:1;
    uint32  user_dma_mode:2; /*0, alloc dma memory by dma module; 1, alloc dma memory by user and wait finish; 2, alloc dma memory by user but not wait finish*/
    uint32  entry_offset:16;
    uint32  desc_index:13;

    uint32 time_stamp[2];
    uint16 op_bmp; /*refer to SYS_USW_DMA_ENCODE_OP_BMP2 or SYS_USW_DMA_ENCODE_OP_BMP*/
    uint8  copy_mode; /*only for write*/

};
typedef struct drv_dma_tbl_rw_s drv_dma_tbl_rw_t;

typedef int32 (* DRV_DMA_WRITE_CB)(uint8 lchip, drv_dma_tbl_rw_t* tbl_cfg);
typedef int32 (* DRV_DMA_READ_CB)(uint8 lchip, drv_dma_tbl_rw_t* tbl_cfg);
typedef int32 (* DRV_DMA_WAIT_DESC_DONE_CB)(uint8 lchip, uint8 is_read, uint32 desc_index);
typedef int32 (* DRV_DMA_TRIGGER_CB)(uint8 lchip, uint32 vld_num);

#define ________HSS__________

/*
   hss15g and hss28g using these address to access hssctl,
   Notice for hss28g only using 4 lanes, so EFGH lane is useless for hss28g
*/
enum drv_hss_prt_addr_e
{
    DRV_HSS_TX_LINKA_ADDR = 0,    /*0*/
    DRV_HSS_TX_LINKB_ADDR,         /*1*/
    DRV_HSS_RX_LINKA_ADDR,         /*2*/
    DRV_HSS_RX_LINKB_ADDR,         /*3*/
    DRV_HSS_TX_LINKC_ADDR,         /*4*/
    DRV_HSS_TX_LINKD_ADDR,         /*5*/
    DRV_HSS_RX_LINKC_ADDR,         /*6*/
    DRV_HSS_RX_LINKD_ADDR,         /*7*/
    DRV_HSS_TX_LINKE_ADDR,          /*8*/
    DRV_HSS_TX_LINKF_ADDR,          /*9*/
    DRV_HSS_RX_LINKE_ADDR,          /*10*/
    DRV_HSS_RX_LINKF_ADDR,          /*11*/
    DRV_HSS_TX_LINKG_ADDR,          /*12*/
    DRV_HSS_TX_LINKH_ADDR,          /*13*/
    DRV_HSS_RX_LINKG_ADDR,          /*14*/
    DRV_HSS_RX_LINKH_ADDR,          /*15*/
    DRV_HSS_COMMON_ADDR = 16,
    DRV_HSS_TX_BC_ADDR,               /*17*/
    DRV_HSS_RX_BC_ADDR,               /*18*/

    DRV_HSS_PLLA_ADDR = 20,           /*20*/
    DRV_HSS_PLLB_ADDR                   /*21*/

};
typedef enum drv_hss_prt_addr_e drv_hss_prt_addr_t;

enum drv_hss_type_e
{
    HSS_I2C_HSS6G,
    HSS_PCIE_HSS15G,
    HSS_PCIE_HSS15G_AEC,
    HSS_PCIE_HSS15G_AET,
    HSS_PCIE_HSS28G,
    HSS_PCIE_HSS28G_AEC,
    HSS_PCIE_HSS28G_AET,
};
typedef enum drv_hss_type_e drv_hss_type_t;


struct drv_hss_param_s
{
    uint8   type;
    uint8   hssid;
    uint8   lane_id;
    uint8   rsv;
    uint32  addr;
    uint16  value;
    uint16  mask;
};
typedef struct drv_hss_param_s drv_hss_param_t;
enum drv_chip_sub_type_e
{
    DRV_CHIP_SUB_TYPE_0,
    DRV_CHIP_SUB_TYPE_1,
    DRV_CHIP_SUB_TYPE_2,
    DRV_CHIP_SUB_TYPE_3,
    DRV_CHIP_SUB_TYPE_4,
    DRV_CHIP_SUB_TYPE_5,
    DRV_CHIP_SUB_TYPE_6,
    DRV_CHIP_SUB_TYPE_7,
    DRV_CHIP_SUB_TYPE_8,
    DRV_CHIP_SUB_TYPE_9,
    DRV_CHIP_SUB_TYPE_MAX
};
typedef enum drv_chip_sub_type_e drv_chip_sub_type_t;

#define DRV_HSS_ADDR_COMBINE(addr_h, addr_l)   (((addr_h)<<6)|(addr_l))

#define DRV_IS_DUET2(lchip)  (DRV_DUET2 == drv_get_chip_type(lchip))
#define DRV_IS_TSINGMA(lchip) (DRV_TSINGMA == drv_get_chip_type(lchip))
#define DRV_IS_TMM(lchip) (DRV_TSINGMA_MX == drv_get_chip_type(lchip))
#define DRV_IS_TMG(lchip) (DRV_TSINGMA_GX == drv_get_chip_type(lchip))
#define DRV_IS_AT(lchip) (DRV_ARCTIC == drv_get_chip_type(lchip))

#define DRV_CHIP_SUB_TYPE(lchip) (drv_get_chip_sub_type(lchip))

#define DRV_FROM_TM(lchip) (drv_get_chip_type(lchip) >= DRV_TSINGMA)
#define DRV_FROM_TMM(lchip) (drv_get_chip_type(lchip) >= DRV_TSINGMA_MX)
#define DRV_FROM_TMG(lchip) (drv_get_chip_type(lchip) >= DRV_TSINGMA_GX)
#define DRV_FROM_AT(lchip) (drv_get_chip_type(lchip) >= DRV_ARCTIC)
#define DRV_NAT_TCAM_MAP(lchip, key_index) drv_lpm_nat_tcam_map_index(lchip, key_index)
#define DRV_FEATURE_MODE_PP     1
/*this struct should be same with ds_mem_type_t*/
enum ds_feature_mode_e
{
   DRV_FEATURE_MODE_PER_DP,
   DRV_FEATURE_MODE_PER_PP,
   DRV_FEATURE_MODE_PER_CORE,
   DRV_FEATURE_MODE_PEER_DP,
   DRV_FEATURE_MODE_PEER_PP,
   DRV_FEATURE_MODE_PER_MAX
};
typedef enum ds_feature_mode_e ds_feature_mode_t;

extern int32 drv_get_enum_type(uint8 lchip, uint32 start, uint32 end, uint32 value);

void* drv_get_table_property_value(uint8 lchip, uint8 type, tbls_id_t tbl_id, uint32 index);

extern uint32 drv_get_const_value(uint8 lchip, drv_constant_t type);

extern int32  drv_field_support_check(uint8 lchip, tbls_id_t tbl_id, fld_id_t field_id);

extern uint8  drv_is_chip(uint8 lchip, drv_chip_series_t chip_type);

extern int32 drv_set_access_type(uint8 lchip, drv_access_type_t access_type);

extern int32 drv_get_access_type(uint8 lchip, drv_access_type_t* p_access_type);

extern int32 drv_get_gchip_id(uint8 lchip, uint8* gchip_id);
extern int32 drv_set_gchip_id(uint8 lchip, uint8 gchip_id);
//extern int32 drv_usw_agent_register_cb(uint8 type, void* cb);
extern int32 drv_get_chip_agent_mode(void);

extern int32 drv_get_platform_type(uint8 lchip, drv_work_platform_type_t *plaform_type);
extern int32 drv_get_host_type (uint8 lchip);
extern int32 drv_get_table_property(uint8 lchip,uint8 type, tbls_id_t tbl_id, uint32 index, void* value);
extern int32 drv_get_field(uint8 lchip, tbls_id_t tbl_id, fld_id_t field_id, void* ds, uint32* value);
extern int32 drv_set_field(uint8 lchip, tbls_id_t tbl_id, fld_id_t field_id, void* ds, uint32 *value);
extern int32 drv_set_field32(uint8 lchip, tbls_id_t tbl_id, fld_id_t field_id, uint32* entry, uint32 value);
extern uint32 drv_get_field32(uint8 lchip, tbls_id_t tbl_id, fld_id_t field_id, void* entry);
extern int32 drv_get_x_field(uint8 lchip, uint8 i_word, uint8 i_start, uint8 i_bits, void* ds, uint32* value);
extern int32 drv_set_x_field(uint8 lchip, uint8 i_word, uint8 i_start, uint8 i_bits, void* ds, uint32 *value);

extern uint32 drv_get_field_value(uint8 lchip, tbls_id_t tbl_id, fld_id_t field_id,  void* ds);
extern int32 drv_install_api(uint8 lchip, drv_io_callback_fun_t* cb);
extern int32 drv_ioctl_api(uint8 lchip, uint32 index, uint64 cmd, void* val);
extern int32 drv_ioctl_bmp_api(uint8 lchip, uint32 index, uint64 cmd, void* val);
//extern int32 drv_ioctl_api_new(uint8 lchip, int32 index, uint32 cmd, void* val);
extern int32 drv_acc_api(uint8 lchip, void* in, void* out);
extern int32 drv_acc_fdb_calc_index(uint8 lchip, void* in, void* out);
extern int32 drv_acc_get_hash_module(uint8 lchip, uint32 tbl_id, uint8* p_module);
extern int32 drv_set_warmboot_status(uint8 lchip, uint32 wb_status);
extern int32 drv_get_warmboot_status(uint8 lchip, uint32* p_wb_status);
extern int32 drv_init(uint8 lchip, uint8 base);
extern int32 drv_deinit(uint8 lchip, uint8 base);
extern int32 drv_sdb_store(uint8 lchip, tbls_id_t tbl_id, uint32 entry_idx, void* p_data, uint32 entry_size, uint8 oper_bmp);
extern int32 drv_sdb_write(uint8 lchip, tbls_id_t tbl_id, uint32 entry_idx, void* p_data, uint32 entry_size, uint8 oper_bmp);
extern int32 drv_usw_ftm_get_entry_num(uint8 lchip, uint32 table_id, uint32* entry_num);

extern int32 drv_usw_ftm_lookup_ctl_init(uint8 lchip);

extern int32 drv_usw_ftm_mem_alloc(uint8 lchip, void* profile_info);

extern int32 drv_usw_ftm_mem_free(uint8 lchip);

extern int32 drv_usw_ftm_get_info_detail(uint8 lchip, drv_ftm_info_detail_t* p_ftm_info);

extern int32 drv_usw_ftm_get_sram_type(uint8 lchip, uint32 mem_id, uint8* p_sram_type);

extern int32 drv_usw_ftm_get_hash_poly(uint8 lchip, uint32 mem_id, uint8 sram_type, uint32* drv_poly);

extern int32 drv_usw_ftm_set_hash_poly(uint8 lchip, uint32 mem_id, uint8 sram_type, uint32 drv_poly);

/* sram type refer to drv_ftm_sram_tbl_type_t*/
extern int32 drv_usw_get_dynamic_ram_couple_mode(uint8 lchip, uint16 sram_type, uint32* couple_mode);

extern int32 drv_ftm_get_mem_info(uint8 lchip, drv_ftm_mem_info_t* p_mem_info);

extern int32
drv_sdb_dump(uint8 lchip, uint8 type, uint32 tbl_id, char* file);
extern int32
drv_sdb_check(uint8 lchip, uint8 type, uint8 recover_en, uint32 tbl_id, char* file);
extern int32
drv_sdb_read_from_hw(uint8 lchip, uint8 enable);
extern int32
drv_sdb_set_stop_store(uint8 lchip, uint8 enable);
extern int32
drv_sdb_show_status(uint8 lchip, uint8 type, char* table_name);
extern int32
drv_sdb_show_changed_table(uint8 lchip, char * tbl_name, uint32 start_time, uint32 end_time);
extern int32
drv_sdb_set_init_done(uint8 lchip);
extern void
drv_sdb_get_table_enable(uint8 lchip, uint32 tbl_id, uint8* enable);
extern int32
drv_sdb_init(uint8 lchip, void* p_cfg);
extern int32
drv_sdb_deinit(uint8 lchip);

extern int32
drv_usw_get_tbl_index_base(uint8 lchip, tbls_id_t tbl_id, uint32 index, uint16 *addr_offset);

fields_t *
drv_usw_find_field(uint8 lchip, tbls_id_t tbl_id, fld_id_t field_id);

extern int32
drv_usw_get_tbl_string_by_id(uint8 lchip, tbls_id_t tbl_id, char* name);

extern int32
drv_usw_get_field_string_by_id(uint8 lchip, tbls_id_t tbl_id, fld_id_t field_id, char* name);

extern int32
drv_usw_get_tbl_id_by_string(uint8 lchip, tbls_id_t* tbl_id, char* name);

extern int32
drv_usw_get_field_id_by_string(uint8 lchip, tbls_id_t tbl_id, fld_id_t* field_id, char* name);

extern int32
drv_usw_get_field_id_by_sub_string(uint8 lchip, tbls_id_t tbl_id, fld_id_t* field_id, char* name);

extern uint32
drv_usw_get_field_id_by_name(uint8 lchip, uint8 lkup_id, uint32 tbl_id, char* key_str, char* field_name);

extern int32
drv_usw_table_get_hw_addr(uint8 lchip, tbls_id_t tbl_id, uint32 index, uint32* hw_addr, uint32 flag);

extern uint32
drv_usw_get_table_type(uint8 lchip, tbls_id_t tb_id);

extern int32
drv_usw_chip_read(uint8 lchip, uint64 offset, uint32* p_value);

extern int32
drv_usw_chip_write(uint8 lchip, uint64 offset, uint32 value);

extern int32
drv_usw_ftm_get_entry_size(uint8 lchip, uint32 table_id, uint32* entry_size);

extern int32
drv_usw_hss_read(uint8 lchip, drv_hss_param_t* param);

extern int32
drv_usw_hss_write(uint8 lchip, drv_hss_param_t* param);

extern int32
drv_usw_cpu_mcu_lock(uint8 lchip, tbls_id_t tbl_id, uint32 op, uint32 flow_flag);
extern int32
drv_usw_cpu_mcu_unlock(uint8 lchip, tbls_id_t tbl_id, uint32 op, uint32 flow_flag);

extern int32 drv_get_field_name_by_bit(uint8 lchip, tbls_id_t tbl_id, uint32 bit_id, char* field_name);
extern uint32 drv_get_chip_type(uint8 lchip);

extern int32 drv_chip_read_hss15g(uint8 lchip, uint8 hssid, uint32 addr, uint16* p_data);
extern int32 drv_chip_write_hss15g(uint8 lchip, uint8 hssid, uint32 addr, uint16 data);
extern int32 drv_chip_read_hss28g(uint8 lchip, uint8 hssid, uint32 addr, uint16* p_data);
extern int32 drv_chip_write_hss28g(uint8 lchip, uint8 hssid, uint32 addr, uint16 data);
extern int32 drv_chip_read_hss(uint8 lchip, uint32 grp_id, uint32 addr, void* p_data);
extern int32 drv_chip_write_hss(uint8 lchip, uint32 grp_id, uint32 addr, void* p_data);
extern int32 drv_ioctl_table_copy(uint8 lchip, tbls_id_t dst_tbl, uint32 dst_idx, tbls_id_t src_tbl, uint32 src_idx);
extern int32 drv_read_efuse_data(uint8 lchip, uint32 offset, uint32 len, uint32* p_value);
extern uint32 drv_get_chip_sub_type(uint8 lchip);
extern int32 drv_field_ioctl_api(uint8 lchip, int32 index, uint64 cmd, void* val);
extern int32 drv_field_ioctl_bmp_api(uint8 lchip, int32 index, uint64 cmd, void* val);
extern uint8 drv_vchip_get_pp_base(uint8 lchip);
extern uint8 drv_vchip_get_core_pp_base(uint8 lchip);
extern uint8 drv_vchip_get_pp_num(uint8 lchip);
extern uint8 drv_vchip_get_pp_bmp(uint8 lchip);
extern uint8 drv_vchip_get_core_num(uint8 lchip);
extern uint8 drv_vchip_get_core_pp_num(uint8 lchip);
extern uint8 drv_get_vchip_pcie_bmp(uint8 lchip);
extern int32 drv_init_vchip(uint8 lchip, uint32 vchip_bmp, uint8 lchip_idx);

extern int32 drv_tcam_write_lock(uint8 lchip);
extern int32 drv_tcam_write_unlock(uint8 lchip);
extern uint32 drv_get_table_max_band(uint8 lchip, uint32 tbl_id);
extern uint16 drv_get_key_width(uint8 lchip, uint32 tbl_id);
extern int32 drv_sdb_store(uint8 lchip, tbls_id_t tbl_id, uint32 entry_idx, void* p_data, uint32 entry_size, uint8 oper_bmp);
extern void* drv_sdb_read(uint8 lchip, tbls_id_t tbl_id, uint32 index, uint32 entry_size, uint8 oper_bmp);
extern uint32 drv_sdb_get_sdb_en(uint8 lchip);
extern int32 drv_set_met_mode(uint8 lchip, uint8 met_ext_mode);
extern int32 drv_sdb_set_tbl_feature_mode(uint8 lchip, uint32 tbl_id, uint8 mode);
extern uint32 drv_sdb_calc_tbl_size(uint8 lchip, uint8 mode);

extern int32 drv_lpm_nat_tcam_map_index(uint8 lchip, uint32 key_index);
extern int32 drv_mem_map(uint8 lchip, uint16 mem_id, uint32 invalid_bmp[]);
extern int32 drv_lpm_tcam_map(uint8 lchip, uint16 mem_id, uint32 invalid_bmp[]);
extern int32 drv_usw_lpm_tcam_init_blknum(uint8 lchip);
extern uint32 drv_usw_get_flow_tcam_entry_num(uint8 lchip, uint16 mem_id);
extern int32 drv_usw_ftm_mapping_drv_hash_poly_type(uint8 lchip, uint8 sram_type, uint32 type, uint32* p_poly);
extern int32 drv_usw_ftm_get_current_hash_poly_type(uint8 lchip, uint32 mem_id, uint8 sram_type, uint32 *poly_type);
extern int32 drv_usw_ftm_get_hash_poly_cap(uint8 lchip, uint8 sram_type, uint32 mem_id, uint8* poly_num, uint32* poly_type);
extern int32 drv_usw_ftm_show_hash_poly(uint8 lchip, uint32 mem_id, uint8 sram_type);
extern int32 drv_usw_ftm_get_tcam_memory_info(uint8 lchip, uint32 mem_id, uint32* p_mem_addr, uint32* p_entry_num, uint32* p_entry_size, drv_ftm_tcam_info_t* tcam_info);
extern int32 drv_sdb_register_dma_write_cb(uint8 lchip, DRV_DMA_WRITE_CB cb);
extern int32 drv_sdb_register_dma_read_cb(uint8 lchip, DRV_DMA_READ_CB cb);
extern int32 drv_sdb_register_dma_wait_done_cb(uint8 lchip, DRV_DMA_WAIT_DESC_DONE_CB cb);
extern int32 drv_sdb_register_dma_trigger_cb(uint8 lchip, DRV_DMA_TRIGGER_CB cb);
extern int32 drv_usw_register_eunit_lock(uint8 lchip, void* cb);
extern int32 drv_usw_set_eunit_lock_en(uint8 lchip, uint8 enable);

extern int32 drv_ioctl_read_tcam(uint8 lchip, drv_ioctl_param_t* p_ioctl_param);  /* only used by program acl other table use without check to ensure performance */
extern int32 drv_ioctl_write_tcam(uint8 lchip, drv_ioctl_param_t* p_ioctl_param);  /* only used by program acl other table use without check to ensure performance */
extern int32 drv_ioctl_remove_tcam(uint8 lchip, drv_ioctl_param_t* p_ioctl_param);  /* only used by program acl other table use without check to ensure performance */
extern int32 drv_ioctl_move_tcam(uint8 lchip, drv_ioctl_param_t* p_src_param, drv_ioctl_param_t* p_dst_param); /* used for acl move */

/* memmap ioctl */
extern int32 drv_ioctl_read_dma(uint8 lchip, uint32 index, uint64 cmd, void* p_val);
extern int32 drv_ioctl_write_dma(uint8 lchip, uint32 index, uint64 cmd, void* p_val);
extern int32 drv_ioctl_mask_write_dma(uint8 lchip, uint32 index, uint64 cmd, void* p_val);
#ifdef __cplusplus
}
#endif
#endif /*end of _DRV_API_H*/
